1. Field of the Invention
The present invention relates to a semiconductor device comprising an enhancement-mode (E-mode) field-effect transistor (FET) and a depletion-mode (D-mode) FET which are operated at a high speed by using a two-dimensional electron gas.
2. Description of the Related Art
In general, the above FETs comprise a semi-insulating gallium-arsenide (GaAs) substrate, an undoped GaAs channel layer, an N-type aluminum-gallium-arsenide (AlGaAs) electron-supply layer, and an N-type GaAs cap layer, which layers are successively formed on the substrate. A threshold voltage Vth of the FET depends on the thickness of a semiconductor layer including the N-type AlGaAs electron-supply layer between the undoped GaAs channel layer and a contacting bottom of a gate electrode.
Furthermore, a logic circuit, e.g., a basic inverter, comprises an enhancement/depletion (E/D) constitution consisting of an E-mode FET and a D-mode FET. In an E/D constitution semiconductor device for such a logic circuit, it is necessary to form the E-mode FET having one threshold voltage and the D-mode FET having another threshold voltage in the same semiconductor substrate.
Accordingly, where the E/D constitution semiconductor device is formed by using FETs operating at a high speed by using two-dimensional electron gas, it is necessary to form the E-mode FET and D-mode FET on the same semi-insulating substrate in such manner that the D-mode FET has a thickness of a semiconductor layer between the undoped channel layer and the contacting bottom of the gate electrode thereof different from that of the E-mode FET.
Such an E/D constitution semiconductor device has been produced by methods proposed, for example, in U.S. Ser. No. 587,967 (Filing date: Mar. 9, 1984) and U.S. Ser. No. 676,359 (Filing Note: Nov. 19, 1984) in the name of the assignee, FUJITSU LIMITED. The proposed methods utilize the additional formation of one or two thin AlGaAs layers and the adoption of a reactive ion etching (RIE) method using an etchant gas comprising CCl.sub.2 F.sub.2, which will etch GaAs very rapidly as compared with AlGaAs. In such an etching, the etching rate for GaAs is about 200 times faster than that for AlGaAs.
In U.S. Ser. No. 587,967 portions in an E-mode FET region of a contact (cap) GaAs layer, an one etching stoppable AlGaAs layer, and a GaAs layer on an AlGaAs electron-supply layer are selectively etched by a wet chemical etching method to form a recess, as shown in FIG. 10. Although the GaAs layer on the AlGaAs electron-supply layer should be competely removed, a portion of the AlGaAs electron-supply layer may be etched in some of the recesses among all of the recesses in a wafer. When an E-mode FET is produced at the partially etched AlGaAs electron-supply layer, the threshold voltage of the E-mode FET varies from a predetermined value, due to variations in the thickness of the AlGaAs electron-supply layer.
In U.S. Ser. No. 676,359 after at least a contact (cap) GaAs layer and an (second) etching stoppable AlGaAs layer are selectively etched in an E-mode FET to form a recess, a reactive ion etching treatment using CCl.sub.2 F.sub.2 gas is performed so as to simultaneously complete grooves for gate electrodes of the E-mode and D-mode FET's. In the etching step, at least the above-mentioned AlGaAs layer in the D-mode FET region is etched and a portion of the AlGaAs electron-supply layer in the E-mode FET region is etched. However, the etch rate for AlGaAs is, in practice, varied, and in the second embodiment, another (first) etching stoppable AlGaAs layer in GaAs layer between the former AlGaAs layer and the electron-supply layer and both the AlGaAS layers should be made to have the exactly same thickness. Such factors cause variations in the thickness of a semiconductor layer between the undoped GaAs layer and the contacting bottom of the gate electrodes, namely, variations in the threshold voltages of the E-mode and D-mode FETs. In short, the proposed producing methods cannot sufficiently attain an exact control of the groove depth for gate electrodes by etching, namely, uniformity of the threshold voltages of the E-mode and D-mode FETs formed in a wafer is relatively low.
For example, when an acceptable variation of the threshold voltage of each of the E-mode and D-mode FETs is .+-.50 mV, a thickness variation is .+-.1 nm corresponding to three atomic layers.